CALL FOR PARTICIPATION |
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The IEEE International Mixed Signals Testing Workshop (IMSTW) is a forum for discussing all aspects of testing, design-for-test and reliable design of integrated mixed signals/technologies, functions, and systems. This includes testing, design verification, and design for manufacturability of monolithic mixed signals/technologies systems (SoC), heterogeneous systems including system-in-package and printed circuit board implementations of mixed-signal functions. The technology spectrum includes analogue, mixed signals, high-speed IO, RF, MEOMS (inc. biochemical and microfluidics), sensor networks, and nanotechnology. Test topics include, but are not restricted to, design-for-test techniques, BIST, fault diagnosis, test generation, online and off-line testing, fault modelling and simulation, design of fault tolerant systems, mixed signals infrastructures, embedded core test, and application specific testing topics. IMSTW is sponsored by the IEEE Computer Society Test Technology Technical Council. |
Program Overview |
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A high-quality program, built from the contributions submitted to both IMSTW and GTW, has been prepared. This joint program comprises seven regular and two poster sessions, with in total thirty five presentations, covering the areas of analogue, mixed-signal, RF, high-speed IO, MEMS, and board test. A panel session on GHz/Gbps testing will present and discuss issues involved in testing electronic circuits running in the multi-GHz clock range and/or including I/O capable of multi-Gbps data rates. Three invited key-note speeches will address the critical test topics of using analogue approaches for testing low-power digital IC’s, GHz/Gbps testing, and the challenges of MEMS testing. |
The Venue |
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The Workshop will take place in the Novotel Vermar Hotel in the city of Póvoa de Varzim. Located near the airport, and with easy access to downtown Porto, Póvoa de Varzim lies in a sandy coastal plain in the northwest region of the country known as Costa Verde. Inland, there are several historic and interesting cities, towns and villages that fascinate the passing tourist and bear testimony of the ancient beginnings of modern Portugal. The social programme includes a visit to Guimarães, the first capital of Portugal in the twelfth century. Its Historic Centre was awarded the status of World Heritage of Humankind by UNESCO in 2001. |
Workshop Registration |
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The registration for the joint IMSTW/GTW’07 event is now open. Advance registrations can be received until the 25th of May, 2007. More details can be found on the website at www.fe.up.pt/imstw07/registration.htm |
Advance Program |
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Monday -- Tuesday -- Wednesday
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9:00 AM
- 10:00 AM |
Opening Session |
9:00 - 9:10 |
Welcome Address |
9:10 - 10:00 |
Invited Talk 1 – Testing Low Power Digital IC's May Require Mixed-Signal Test Solutions
Joan Figueras, Universitat Politècnica de Catalunya |
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10:00 AM
- 10:20 AM |
Poster Session 1 |
P1.1 |
Wavelet – Neural Network to Analog Parametric Fault Circuit Location
Damian Grzechca, Silesian University of Technology, Poland
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P1.2 |
Implementing a Tuning Algorithm for Continuous-time Filters in a Digital Environment
Gianvito Matarrese, Cristoforo Marzocca, Francesco Corsi, Dipartimento di Elettrotecnica ed Elettronica - Politecnico di Bari, Italy |
P1.3 |
Estimation and Adaptive Correction of PA’s Nonlinearities
José Machado da Silva, Pedro Mota, John Long, INESC Porto, Universidade do Porto, Portugal, TUDelft, The Netherlands |
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10:20 AM - 10:50 AM BREAK POSTER SESSION 1 |
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10:50 AM
- 12:30 PM |
Session 1 – Analogue Testing |
S1.1 |
Functional Test Compaction by Statistical Modelling of Analogue Circuits
Nourredine Akkouche, Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, TIMA Laboratory, France |
S1.2 |
Testing SET Effects in a CMOS Operational Amplifier
Jose Huertas, John Espinosa, Gloria Huertas, Jaime Velasco-Medina, Raoul Velazco, Universidad de Sevilla, Spain, Universidad del Valle, Colombia, IMSE-CNM, Spain, TIMA Laboratory, France |
S1.3 |
A Tool for Single Fault Diagnosis in Linear Analog Circuits
José Augusto, Carlos Almeida, Universidade de Lisboa - FCUL and INESC -ID, IST-UTL and Inesc-ID, Universidade de Lisboa - FCUL, Dep. de Física, Portugal |
S1.4 |
Impact of Circuit Parameter Derivative Calculation on Estimation of Statistical Variables for Analog Fault Detectability Evaluation
Alkiviades Hatzopoulos, Dimitrios Papakostas, Aristotle University of Thessaloniki, A.T.E.I.Th., Greece |
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12:30 PM
- 2:00 PM LUNCH |
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2:00 PM
- 3:15 PM |
Session 2 – Mixed-Signal Test |
S2.1 |
Noise-insensitive BIST to Measure Small Phase Delays
Stephen Sunter, Aubin Roy, LogicVision, Inc., USA
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S2.2 |
Gaps in Timing Margining Test for Serial Interfaces: A Case Study
Anne Meixner, Dongwoo Hong, Benoit Provost, Intel, USA, University of California, Santa Barbara, USA |
S2.3 |
A Built-in Methodology for Resemblance Gathering in RKII Networks
Manuel Cândido Santos, Vitor Grade Tavares, José Machado da Silva, Sebastian Tabarce, FEUP/DEEC - University of Porto, INESC Porto, Portugal |
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3:15 PM - 3:45 PM BREAK |
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3:45 PM
- 5:25 PM |
Session 3 – RF Testing |
S3.1 |
Optimization of Behavioral Level Design Validation Test Bench for Production Testing of AMS & RF SoCs
Yves Joannon, LCIS INPG, France |
S3.2 |
Using Signal Envelope Detection for RF MEMS Switch Testing
E. Simeu, H. N. Nguyen, P. Cauvet, S. Mir, L. Rufer, R. Khereddine, TIMA Laboratory, NXP Semiconductors, France
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S3.3 |
Built-In Test of RF Receivers Using RF Amplitude Detectors
Chaoming Zhang, Ranjit Gharpurey, Jacob Abraham, University of Texas at Austin, USA |
S3.4 |
Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems
Rajarajan Senguttuvan, Abhijit Chatterjee, Vishwanath Natarajan, Georgia Institute of Technology, USA |
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6:00 PM
WELCOME RECEPTION |
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9:00 AM - 9:40 AM |
Invited Talk 2 – Multi-GHz and Multi-Gbps Testing Issues |
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To be defined |
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9:40 AM
- 10:20 AM |
Session 4 – Board and System Level Test |
S4.1 |
Embedded Test Controller for Board and System Level Remote Testing
Jari Hannu, Tuomas Happonen, Markku Moilanen, University of Oulu, Finland |
S4.2 |
A Built-in Debugger for 1149.4 Circuits
Manuel Felgueiras, Gustavo Alves, José Ferreira, ISEP, University of Porto, Portugal |
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10:20 AM - 10:50 AM BREAK |
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10:50 AM - 12:30 PM |
Session 5 – GHz/Gbps Testing |
S5.1 |
Testing SerDes ICs Beyond 4 Gbps – New Priorities
Stephen Sunter, Aubin Roy, LogicVision, Inc., USA |
S5.2 |
A Novel Built-in Test Technique for Phase/Frequency Modulated RF Transmitters
Hyun Choi, Donghoon Han, Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, USA |
S5.3 |
Design and Implementation of Low Noise and High Speed Multilayer Test Board with High Performance 3D-EBG Structure
Kijae Song, Samsung Electronics, Koreay |
S5.4 |
MEMs Switches and SiGe Logic for Multi-GHz Loopback Testing
David C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John Mckillop, Georgia Institute of Technology, Atlanta, USA, IBM, Bromont, Canada, TeraVicta, Austin, USA |
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12:30 PM
- 2:00 PM LUNCH |
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2:00 PM
- 3:45 PM |
Panel Discussion |
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Organizer: Stephen Sunter, LogicVision, USA |
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4:00 PM
SOCIAL EVENT |
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June 20, 2007 (Wednesday) |
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9:00 AM - 9:40 AM |
Invited Talk 3 - The Challenges of MEMS Testing |
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Shawn Blanton, Carnegie Mellon University |
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9:40 AM
- 10:20 AM |
Poster Session 2 |
P2.1 |
A Novel Binary Search Method for Characterizing Hysteresis Featured in Integrated Circuits
Weishu Wu, Texas Instruments |
P2.2 |
Mixed-signal Design of Dynamic Delay Buffers to Improve Tolerance to Power Supply and Temperature Variations
Jorge Semião, João Paulo Teixeira, Isabel Teixeira, Fabian Vargas, Juan J. Rodriguez-Andina, Judit Freijedo, Escola Superior de Tecnologia - Universidade do Algarve, IST/INESC-ID, Portugal, Catholic University - PUCRS, Brazil, University of Vigo, Spain |
P2.3 |
Considerations for FPGA Integration into the ATE Device Interface Board
Ian Grout, Thomas Oshea, Jeffrey Ryan, University of Limerick, Ireland |
P2.4 |
Layout-Oriented Fault Analysis for DRAM Design Components
Martin Versen, Jelena Kneževic, Sergio Montoya, Torsten Coym, Wolfgang Vermeiren, Bernd Straube, Qimonda AG, Fraunhofer Inst. für Int. Schaltungen (IIS), Germany |
P2.5 |
Accurate Linearity Testing of A/D Converters in the Presence of Ground Bounce Noise
Shalabh Goyal, Abhijit Chatterjee, Georgia Institute of Technology, USA |
P2.6 |
White Noise Signal Generator for ADC Testing
Josef Vedral, CTU FEE Prague, Czech Republic |
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10:20 AM - 10:50 AM BREAK POSTER SESSION 2 |
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10:50 AM - 12:30 PM |
Session 6 – MEMS Testing |
S6.1 |
Inductive Fault Analysis for DNA Sensor Arrays
Daniela de Venuto, Politecnico di Bari, Italy |
S6.2 |
Self-Testing of Micro-Electrode Array Implemented as a Bio-Sensor
Hongyuan Liu, Lancaster University, United Kingdom |
S6.3 |
Capacitive MEMS Accelerometers Testing Mechanism for Auto-calibration and Long-term Diagnostics
Luís Rocha, Lukas Mol, Edmond Cretu, Reinoud Wolffenbuttel, José Machado da Silva, Faculdade de Engenharia da Universidade do Porto, Portugal, Delft University of Technology, The Netherlands, University of British Columbia, Canada, INESC Porto, Portugal |
S6.4 |
A Fault-Tolerant MEF Peptide Synthesizer Using Sense-Electrode
Xiao Zhang, Hans Kerkhoff, Frédérick Mailly, Pascal Nouet, Hongyuan Liu, Andrew Richardson, TDT, CTIT, University of Twente, The Netherlands, LIRMM, France, Lancaster University, United Kingdom |
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12:30 PM
- 2:00 PM LUNCH |
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2:00 PM
- 4:05 PM |
Session 7 – ADC Test |
S7.1 |
A Simple Method for Linearity Testing of ADCs Using Nonlinear Test Stimuli
Esa Korhonen, Juha Kostamovaara, University of Oulu, Electronics Laboratory, Finland |
S7.2 |
Postprocessing Measurement Data---Are You Using the Correct Algorithm?
Carsten Wegener, Infineon Technologies AG, Germany |
S7.3 |
Fully-Efficient ADC Test Technique for ATE with Low Resolution Arbitrary Wave Generators
Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azäis, Michel Renovell, Mariane Comte, NXP, LIRMM, LIRMM, France |
S7.4 |
Simple Evaluation of the Non-linearity Signature of an ADC Using a Spectral Approach
Eduardo Peralias, M. Angeles Jalon, Adoracion Rueda, IMSE-CNM, Universidad de Sevilla, Spain |
S7.5 |
A Methodology for Structural Test of Folded ADCs
Roman Mozuelos, Yolanda Lechuga, Mar Martinez, Salvador Bracho, University of Cantabria, Spain |
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4:05 PM
- 4:20 PM CLOSING SESSION |
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More Information |
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Program
Information
Prof. Marcelo Lubaszewski
UFRGS Federal University
90035-190 Porto Alegre RS, Brazil
Tel.: +55 51 3316 3516
Fax: +55 51 3316 3293
E-mail : luba@ece.ufrgs.br
Bozena Kaminska
Simon Fraser University
Burnaby, BC, Canada V5A 1S6
Tel. : +1 604 2916855
Fax: +1 604 2914951
E-mail: kaminska@sfu.ca
General Information
José Machado da Silva
Faculty of Engineering, University of Porto
4200-465 Porto, Portugal
Tel.: +351 225081796
Fax: +351 225081443
E-mail: jms@fe.up.pt
Local Information
J. Martins Ferreira
Faculty of Engineering, University of Porto
4200-465 Porto, Portugal
Tel.: +351 225081889
Fax: +351 225081443
E-mail: jmf@fe.up.pt
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Committees |
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Organizing
Committee
General Chair
J. Machado da Silva, U. Porto, Portugal
Program Vice-Chairs
A. Richardson, U. Lancaster, UK
C. Su, U. National Chiao Tung, Taiwan
Publicity Chair
B. Courtois, TIMA Labs, France
Publications Co-Chairs
J. C. Alves, U. Porto, Portugal
J. S. Augusto, U. Lisboa, Portugal
Program
Committee
J. Abraham, U. Texas, USA
K. Arabi, PMC Sierra, Canada
F. Azais, LIRMM, France
G. Bell, SLI Institute, UK
I. Bell, U. Hull, UK
J. Carbonero, STMicroelectronics, France
L. Carro, UFRGS, Brazil
A. Chatterjee, Georgia Tech, USA
K.-T. Cheng, UCSB, USA
S. Demidenko, Massey U., New Zealand
D. De Venuto, Polytechnic of Bari, Italy
J. Figueras, UPC, Spain
C. Force, Texas Instruments, USA
D. Goodman, Ridgetop, USA
G. Gronthoud, NXP Semi., Netherlands
J.-L. Huang, National Taiwan U., Taiwan
J. Huertas-Diaz, IMSE-CNM/CSIC, Spain
D. Keezer, Georgia Tech., USA
H. Kerkhoff, MESA/U. Twente, Netherlands
L. Milor, Georgia Tech., USA
S. Mir, TIMA Labs, France
F. Novak, Josef Stefan Inst., Slovenia
A. Osseiran, Edith Cowan U., Australia
J. Pineda, NXP Semi, Netherlands
M. Renovell, LIRMM, France
K. Roy, U. Purdue, USA
A. Rueda, U. Sevilla, Spain
S. Sattler, Infineon, Germany
M. Slamani, IBM, USA
M. Soma, U. Washington, USA
B. Straube, Fraunhofer IIS/EAS, Germany
S. Sunter, LogicVision, Canada
P. Teixeira, IST / INESC-ID, Portugal
C. Wegener, U. College Cork, Ireland
Ex-Officio
A. Ivanov, U. British Columbia, Canada
Liaisons
IEEE: B. Kaminska, USA
IEEE Europe: J. Figueras, Spain
IEEE Asia-Pac: C. Su, Taiwan
IEEE Latin-America: M. Lubaszewski, Brazil
IEEE North-America: S. Sunter, Canada
Local
Organization
Finance: J. C. Ferreira (U. Porto)
Audiovisuals: H. Mendonça (U. Porto)
Industry liaisons: J. S. Matos (U. Porto) |
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The 13th International Mixed Signals Testing Workshop (IMSTW'07) is
sponsored by the Institute of Electrical and Electronics Engineers
(IEEE) Computer Society's Test Technology Technical Council (TTTC), and
organized by University of Porto.
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